About the role
AI summarisedThis internship offers hands-on experience in custom IC layout engineering, focusing on physical design of integrated circuits using industry-standard EDA tools. Interns will work on real projects involving floor-planning, device placement, signal routing, and PPA optimization for Foundation IP, Analog IP, or RFIC designs in CMOS technology. The role is ideal for students passionate about microchip design and problem-solving.
FablessOnsiteChip Design
Key Responsibilities
- Get a behind-the-scenes look at how microchips are designed and implemented from scratch
- Learn the essentials of Physical Design (aka Layout) for Integrated Circuits
- Be part of a passionate team working on cutting-edge Foundation IP, Analog IP, or RFIC using the latest CMOS technology
- Work on live assignments: floor-planning, device placement, signal routing, debugging, and more
- Collaborate with experts and other interns to optimize chips for Power, Performance, and Area (PPA)
Requirements
- You’re currently studying Electrical, Electronic, or Material Science Engineering
- You love physics, MOS devices, and figuring out how things work
- You’re a hands-on problem solver who enjoys cracking tough challenges
- You’re self-driven, a great communicator, and ready to learn