About the role
AI summarisedLead a team of Static Timing Analysis (STA) engineers to ensure timing closure for high-frequency, low-power ARM-based CPU and MCU designs. Collaborate with Physical Design, Architecture, and Logic Design teams to resolve Place & Route timing issues, derive STA signoff corners, and optimize Power, Performance, and Area (PPA) for advanced technology nodes below 4nm. Drive STA methodology and signoff to achieve optimal silicon yield and aging performance.
FablessOnsiteChip Design
Key Responsibilities
- Close high frequency, low power, multi-hierarchy ARM based CPU and MCU Design
- Work with Physical Design to close on Place & Route related timing issues
- Analyze timing from synthesis to verify constraints
- Work with Architects and logic designers to generate and verify timing constraints
- Derive STA Signoff corners and PVT to achieve best possible silicon yield and aging requirement
Requirements
- Good Knowledge of ARM CPU Architecture and Design
- > 10 years of STA experiences
- Expertise in DVFS
- Expertise in advanced tech node, <4nm
- Expertise in STA Signoff methodology
- Passionate about Optimizing Power, Performance and Area of newest ARM CPU