About the role
AI summarisedThe Engineer/Staff Engineer – Chip Physical Verification Engineer will support MediaTek's physical sign-off flow for SOC designs at advanced technology nodes. Responsibilities include performing full-chip physical verification sign-off (DRC, LVS, ANT, ERC, ESD, PERC), collaborating with Place & Route and IP teams to resolve layout issues, coordinating with manufacturing on DRC concerns, and developing automation solutions to improve tape-out efficiency. The role involves reporting on physical verification issues and enabling technology for successful tape-out.
FablessOnsiteChip Design
Key Responsibilities
- Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out
- Co-work with Place & Route team to resolve full-chip layout integration issues
- Coordinates with internal IP owners on IP related issues
- Coordinates with Manufacturing Team on DRC related issues
- Provide automation solutions to improve efficiency in tape-out flow
Requirements
- Bachelor/master’s degree in electrical/Electronic Engineering/Computer Science
- Familiar with IC Design front-to-backend flow
- Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
- Proficient in script programming, such as Python, TCL, Perl, or C-shell