About the role

AI summarised

The Custom Layout Engineer (Senior) is responsible for leading physical design implementation of Foundation IP, Analog IP, and RFIC across advanced process nodes and multiple foundries. This role involves end-to-end ownership of layout tasks including floorplanning, automation, verification, and cross-functional collaboration to ensure high-quality, timely delivery. The engineer will drive layout automation flows and optimize designs for power, performance, and area while mentoring and contributing to team success.

FablessOnsiteChip Design

Key Responsibilities

Undertake the role of layout engineer for day-to-day project execution of a variety of layout design implementation, including but not limited to Layout Automation, APR for digital design, Workflow Scripting, Foundation IP (IO/ESD), Analog IP and RFIC, across multiple process nodes and diversified foundries
Collaborate with process-oriented or project-oriented multi-functional teams in delivering the physical design portion of IP, test-chip, RFIC or SoC
Be the DRI (Directly Responsible Individual) for the tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning layout construction, physical verification and QA flow sign-off
Be the DRI for layout automation flow, including APR layout implementation and sign-off, layout automation utility development, enhancement and flow sign-off
Provide timely project status updates and proactively anticipate and mitigate potential execution pitfalls to ensure smooth and high-quality delivery for each project
Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area
Achieve good quality layout, work efficiently and effectively with schedule in mind

Requirements

Bachelor’s degree in Electrical, Electronic Engineering, or related field
More than 6 years of direct experience in scripting, APR flow, custom Foundation IP and/or RF/Analog layout implementation
Hands-on experience in advanced CMOS technologies (FinFETs/GAA)
Highly proficient in technical knowledges related to: Foundry DRM of advanced CMOS technologies, design for manufacturability (DFM), floorplanning techniques for hierarchical layout designs, SI/PI, EM/IR and ESD backend implementation flows
Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow
Proficient in Cadence/Synopsys layout editor, APR flow (Innovus/FusionCompiler), and physical verification tools; analytical and skillful in debugging physical verification such as DRC/LVS/ERC/ANT/PERC and all other verifications
A proven layout engineer with effective cross-team communication and strong time management skills
Strong passion in learning, problem solving, and decision-making skills
Proficient in IO/ESD layout and familiar with the layout requirement is a plus
Scripting skills in languages such as SKILL, Tcl, Python, Perl, or C-shell are a plus