About the role
AI summarisedThe Engineer/Staff Engineer – Multi-Dies Physical Verification Engineer will join MediaTek's Chip Physical Verification team to define and enable physical sign-off flows for SoC and Multi-Dies (3D IC) designs. The role focuses on ensuring first-time success in product tape-out by developing and implementing verification technologies at advanced process nodes. Responsibilities include collaborating with package and ESD teams, resolving integration issues, providing automation solutions, and reporting on tape-out PV issues.
FablessOnsiteChip Design
Key Responsibilities
- Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out
- Co-work with Package Design Team to resolve Multi-Dies integration issues
- Co-work with ESD Team to run 3D_PERC flow
- Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD)
- Provide automation solutions to improve efficiency in tape-out flow
Requirements
- Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
- Familiar with 3D IC Design, like CoWoS, SoIC, EMIB etc.
- Familiar with IC Design front-to-backend flow
- Preferably well-versed in Calibre