About the role
AI summarisedThe Senior/Staff Physical Design Engineer at MediaTek will lead the physical design implementation of advanced process chips at 6nm/4nm/3nm and below, coordinating synthesis, APR, PV, floorplanning, and tapeout activities across multiple blocks and teams. This role involves block-level ownership, top-level chip assembly, and schedule management for SoC physical design delivery.
FablessOnsiteChip Design
Key Responsibilities
- IC physical design of 6nm/4nm/3nm and below world leading advanced process chip, from RTL to GDS
- Block coordinator role for Synthesis/APR/PV tasks of more than 10 blocks, solving the critical issue and give the solution to block owners
- TOP role for the complicated hierarchical chip (more than 20 million instances plus 1000+ macros), doing floorplan, partition and assembly etc
- PD PM role to coordinate with Frontend and Signoff team about on time delivery of the SoC PD tasks, responsible for full chip PD schedule and tapeout
Requirements
- Tomorrow built by you.