About the role
AI summarisedJoin Marvell and contribute to the essential building blocks of data infrastructure by focusing on high-speed I/O circuit layout and verification using advanced process nodes.
FablessOnsite
Key Responsibilities
- Perform physical layout and verification of high-speed I/O circuits, General Purpose I/Os, and ESD structures using the latest process nodes with Cadence tools.
- Collaborate with ESD leads to support worldwide Marvell in IP/SoC ESD/LUP DRC/ERC reviews.
- Work with the CAD team to implement ESD/LUP rules for various process nodes.
- Assist in releasing I/O IP libraries and conducting peer-to-peer layout quality checks based on project guidelines.
- Contribute to the team through tool testing, script development, flow documentation, and training.
- Stay current with technology and tool developments to bring new ideas to the team.
Requirements
- Bachelor’s or Master's degree in Computer Science, Electrical Engineering, or a related field.
- At least 3+ years of related professional experience.
- Good understanding of semiconductor and circuit design, including analog mixed-signal layout best practices.
- High level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- High level proficiency in interpreting CALIBRE DRC, ERC, and LVS reports.