About the role
AI summarisedJoin Marvell to work with local and global teams on the physical design of complex chips. This role involves ensuring efficient and robust design processes by collaborating across disciplines and providing technical leadership.
FablessOnsite
Key Responsibilities
- Collaborate with diverse design teams (Digital/RTL/Analog) to ensure timely design convergence and integration.
- Implement and support multi-voltage designs through all implementation stages (place and route, static timing, physical verification) using industry standard EDA tools.
- Partner with RTL design teams to drive assembly and achieve final design closure.
- Provide technical direction, coaching, and mentoring to junior employees and colleagues to ensure successful project outcomes.
- Develop scripts in Shell, Python, and TCL to automate tasks and enhance productivity.
Requirements
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of progressive experience in back-end physical design and verification.
- Expertise in full-chip & sub-hierarchy integration.
- Proven experience integrating and taping out large designs within a digital design environment.
- Strong understanding of RTL to GDS flows and methodology.
- Proficiency in scripting languages including Perl, TCL, and Python.
- Solid understanding of digital logic and computer architecture.
- Knowledge of Verilog.