About the role
AI summarisedJoin a global team at Marvell to contribute to the physical design of complex chips and develop robust design methodologies. This role involves hands-on triage of workflows, running advanced simulations, and performing critical sign-off checks to ensure the physical view of the chip is optimized and ready for the next stage.
FablessOnsite
Key Responsibilities
- Run RTL code through synthesis and Place and Route (PnR) tools to generate the physical view of the chip.
- Analyze performance through timing analysis and verify a robust power grid using EMIR analysis.
- Review completed design runs for errors or implement optimizations based on successful outcomes.
- Contribute to the physical design of complex chips and enhance the overall design process methodology.
Requirements
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in physical design with a focus on block-level PNR.
- Experience working with advanced CMOS process nodes (e.g., 7nm, 5nm, or below).
- Proficiency with industry-standard EDA tools including Cadence Genus, Innovus, Synopsys Design Compiler, IC Compiler, and Fusion Compiler.