About the role
AI summarisedThe Senior/Staff Engineer in Technical Management for Design Verification leads the development and execution of verification strategies at module, IP, and SoC levels. This role involves creating test plans, building verification environments and IPs, implementing coverage-driven randomized tests, and ensuring functional and code coverage closure. The engineer provides hands-on debugging expertise in UVM, SystemVerilog, Verilog, and SystemC, with specialization in low power and formal verification methodologies.
FablessOnsiteChip Design
Key Responsibilities
- Develop verification environment/testbench in Module/IP/SOC level
- Develop verification IP and reference model
- Implement test with randomization based coverage driven verification methodology
- Implement functional and functional/code coverage closure
Requirements
- Bachelor's/Master's Degree in EEE/Computer/IC design
- 4-10 years verification experiences
- IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
- Strong experience and debugging ability on SystemVerilog/UVM
- Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
- Experience on Low Power and formal verification is a plus
- Strong in UNIX scripting with Python, Perl, makefile, Cshell
- Quick to learn new technology
- Singaporeans and Singapore Permanent Residents are preferred