About the role

AI summarised

The Senior / Staff Physical Verification CAD Engineer collaborates with PDK and QA teams to develop, maintain, and debug rule decks for DRC, LVS, ANT, ERC, LPE, and ESD across various process technologies. They implement physical verification and layout implementation flows, perform full-chip verification, and create automation scripts using C-shell, Python, and Perl. The role requires expertise in advanced packaging technologies such as CoWoS and EMIB, proficiency in verification tools like Calibre and ICV, and strong scripting and UNIX/Linux skills.

FablessOnsiteChip Design

Key Responsibilities

Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
Develop layout implementation flow and physical verification flow
Co-work with QA team to reduce the PDKs/Rule deck defects
Perform full-chip physical verification such as debugging DRC/LVS/ERC
Implement automation scripts in C-shell, Python and Perl

Requirements

Bachelor/Master’s Degree in Electrical / Electronics Engineering / Computer Science
Familiar with IC Design front-to-backend flow
Familiar with interposer design, TSV technology and chip stacking techniques such as CoWoS or EMIB with 2.5D and 3D ICs experiences
Preferably well-versed in Calibre, ICV
Proficient in script programming, such as, Tcl, Perl or C-shell
Proficient in UNIX (Linux) platforms
Strong communication skills, problem solving and analytical skills