Marvell

Staff Analog Layout Engineer

Marvell
Fabless SemiconductorSingaporeOnsitePosted 4 weeks ago

About the role

AI summarised

Join a global team at Marvell to play a crucial role in the project lifecycle of cutting-edge semiconductor designs. This role involves running simulations and verifications using Cadence Virtuoso, collaborating closely with designers to refine and debug analog circuits until they meet stringent specifications.

FablessOnsite

Key Responsibilities

  • Run simulations and verifications using Cadence Virtuoso in collaboration with global teams across multiple locations.
  • Collaborate closely with the designer to iteratively refine and debug analog designs until specifications are met.
  • Serve as a key contributor throughout the project lifecycle, from floorplan to delivery and support.
  • Assume ownership of tasks ranging from individual cells to functional blocks, macros, or full chips.
  • Participate in routine technical meetings, providing progress updates and presenting solutions to global teams.

Requirements

  • Fundamental understanding of electrical concepts, likely gained through a degree in Electrical Engineering.
  • Proficiency in using CAD tools for implementing microelectronic layers beyond the schematic level.
  • Proven track record delivering high-speed or precision analog circuits.
  • Experience preferably across multiple process nodes.
  • Ownership through the full development cycle: floorplan, layout, verification, delivery, and support.
  • Excellent communication skills to present updates to global teams across different time zones.