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Marvell

Technical Director, Physical Design

Marvell
Fabless SemiconductorSingaporeOnsitePosted 4 weeks ago
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About the role

AI summarised

As a senior leader in the central physical design team, you will shape the long-term vision for physical design capabilities and infrastructure while leading RTL-to-GDSII implementations for multiple complex SoC programs. This role requires providing strategic technical direction, mentoring teams, and driving the adoption of next-generation physical design methodologies.

FablessOnsite

Key Responsibilities

  • Lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, CTS, timing closure, SI signoff, and physical verification (DRC/LVS).
  • Provide strategic technical leadership to physical design teams, ensuring successful and timely tapeouts of high-performance SoCs.
  • Mentor and develop engineering talent, fostering a culture of innovation and continuous improvement within the physical design organization.
  • Drive cross-functional collaboration with design teams to influence architectural decisions and ensure successful project execution.
  • Drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity.
  • Manage project schedules, resources, and risks in alignment with business goals and customer requirements.
  • Represent the physical design function in cross-organizational and executive-level discussions regarding technology and product strategy.

Requirements

  • 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles.
  • Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Proven track record leading and scaling physical design teams through complex SoC projects to successful tapeouts.
  • Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges.
  • Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
  • In-depth knowledge of modern EDA tools and flows.
  • Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency.