About the role
AI summarisedThis is an entry-level Verification Engineer role focused on developing and maintaining UVM-based verification environments for DDR PHY IP. The engineer will write and execute test plans, debug simulation failures, and collaborate with design teams to ensure silicon success. The role requires foundational knowledge in digital design, SystemVerilog, UVM, and scripting, with preferred exposure to DDR memory protocols and simulation tools.
FablessOnsiteEngineering
Key Responsibilities
- Develop and maintain UVM-based verification environments for DDR PHY IP
- Write and execute test plans, directed and constrained-random tests, and functional coverage models
- Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues
- Create and maintain verification collateral, including testbenches, checkers, and scoreboards
- Perform regression runs, track functional coverage, and ensure full design verification closure
- Contribute to automation scripts for regression, data analysis, and verification efficiency improvements
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Strong understanding of digital design fundamentals (clocking, timing, state machines, analog design basics)
- Experience with SystemVerilog and UVM (academic or internship exposure preferred)
- Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
- Basic understanding of DDR memory protocols and PHY architecture is a plus
- Proficiency in scripting languages (Python, Perl, or TCL) for automation
- Excellent analytical, debugging, and communication skills
- Enthusiasm for learning and problem-solving in a collaborative, fast-paced environment