Qualcomm

Engineer, Senior (Process Development - Interconnect Plating)

Qualcomm
Fabless SemiconductorSingapore, Central Singapore, SingaporeOnsitePosted 1 week ago

About the role

AI summarised

The Senior Engineer in Process Development - Interconnect Plating is responsible for leading the development, qualification, and high-volume production transfer of new interconnect plating processes and technologies. This role involves driving process innovation, ensuring manufacturability and yield targets, coordinating technology transfer from pilot to production, and serving as a technical expert in a semiconductor wafer-level packaging environment. The position requires strong analytical, project, and communication skills to support cross-functional teams in achieving business and launch goals.

FablessOnsiteHardware Engineering

Key Responsibilities

  • Define process requirements, success criteria, design-of-experiments (DOE), and characterization plans
  • Drive root-cause analyses, failure mechanism studies, and improvement loops to achieve performance, yield, and reliability targets
  • Translate product requirements into process specifications and control strategies
  • Work with project leader on technology transfer from pilot line to high-volume manufacturing
  • Lead and drive technical discussions for onsite process transfer activities, including documentation (PFMEA), training, process replication, and equipment matching
  • Work with equipment team on equipment setup and process cluster on establishing critical process windows, statistical control limits, and ramp-readiness criteria
  • Coordinate and report ramp performance tracking (yield, scrap, cycle time, tool capability) and drive closure of gaps
  • Develop new and impactful ideas, materials, solutions, and/or procedures for product fabrication process and technology meeting business goals and launch schedule with competitive manufacturing costs

Requirements

  • Bachelor’s or Master’s degree in Engineering (Materials Science, Chemical Engineering, Chemistry or related fields)
  • 4+ years of experience in Interconnect Plating process engineering, process development, or as process engineer in a high-volume wafer level package manufacturing fab
  • Strong skills in DOE, SPC, data analytics, FMEA, and troubleshooting
  • Excellent communication, technical documentation, and stakeholder management skills
  • Resourceful with critical thinking in problem solving
  • Project and priority management skills
  • Experience in semiconductor, MEMS, packaging, or high-volume manufacturing
  • Familiarity with yield engineering, reliability mechanisms, and failure analysis as well as use of statistical tools, DOE, PFCP/PFMEA, etc.
  • Experience with scale-up from R&D → Pilot → HVM
  • Knowledge of Lean, Six Sigma, or structured problem-solving (8D, DMAIC)
  • Able to multi-task, set priorities and meet critical deadlines
  • Maintain open communication
  • Able to attend training program overseas at sister’s fab for up to 1 year