About the role

AI summarised

The Staff Design Verification Engineer at AMD will contribute to the PLL team by driving design verification efforts from specification to silicon. Responsibilities include developing RTL and firmware validation, creating verification architectures, supporting silicon bring-up and post-silicon debug, and collaborating with RTL design teams to ensure functional correctness. The role requires strong analytical skills, initiative, communication abilities, and mentorship capabilities, with preferred experience in high-speed interfaces, power and clock domains, analog modeling, and industry-standard ASIC CAD tools.

FablessOnsiteEngineering

Key Responsibilities

Analyze complex verification and digital design problems and propose verification / micro-architecture solutions
Drive/develop ASIC verification flows and scripts
Work with the RTL Design team to ensure functional correctness and coverage
Support silicon bring-up and diagnostics
Support Post-silicon debug, root cause bug, provide solution or workaround

Requirements

Excellent analytical and critical thinking skills along with attention to details
Must be an initiative-taker, able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic team-first mentality
Ability to provide mentorship and guidance to junior engineers
Proven experience in design verification from specification to successful silicon
Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in behavior modeling for Analog Circuits
Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc.
Progressive experience in RTL Design
Bachelors or Masters Degree in Computer Engineering/Electrical Engineering