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Micron Technology

Engineer, Product & System Engineering (Media Health Manufacturing), Heterogenous Integration - High Bandwidth Memory

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 4 months ago
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About the role

AI summarised

Join the High Bandwidth Memory (HBM) Product & System Engineering Media Health team to drive manufacturing and product activities for Micron’s latest HBM products across DRAM, Interface die, and stacked configurations. You will be part of a high-performing team focused on achieving Best-In-Class KPIs: Quality, Cost, Cycle Time, and Scale through advanced technical problem-solving.

IDMOnsiteHIG

Key Responsibilities

  • Ensure optimized test coverage across current and future HIG HBM design architectures and process nodes for high-volume manufacturing efficiency.
  • Develop, validate, characterize, and qualify next-generation HBM products to ensure reliability and market readiness.
  • Provide design verification support for new products, including in-depth circuit debugging using CAD tools and Verilog simulations.
  • Drive manufacturing test flow development, validation, and improvement to reduce test time and enhance product quality.
  • Improve manufacturing test yields (Device Issues from DRAM, Interface, and Stacked Die) and reduce overall cost through technical intervention.
  • Conduct root cause analysis and resolution for manufacturing test flow issues, quality concerns, and RMA device problems.
  • Promote innovation and drive technical changes to maintain a competitive advantage in the HBM market.
  • Collaborate cross-functionally with Fab, Product Leads, Design, Technology Development, and Test Solution Engineering teams to achieve strategic objectives.

Requirements

  • Proven experience in Product & System Engineering within High Bandwidth Memory (HBM) or related advanced memory technologies.
  • Strong technical capability in manufacturing test flow development and validation for high-volume production.
  • Demonstrated ability to improve device/stacked yield through in-depth circuit debug and test coverage optimization.
  • Experience driving DFT (Design for Test) strategies to enhance cost, cycle time, and quality.
  • Proficiency in cross-functional collaboration with design, fab, and test teams.
  • Ability to make technical decisions regarding risk analysis and project prioritization in a fast-paced environment.