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Qualcomm

Senior Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)

Qualcomm
Fabless SemiconductorSingapore, Central Singapore, SingaporeOnsitePosted 2 months ago
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About the role

AI summarised

The Senior Staff R&D Design Technology Integration Engineer leads technology integration for advanced semiconductor packaging, focusing on bump, die sort, and backend processes for Si/GaAs devices. This role involves cross-functional collaboration with design, packaging, foundry, and OSAT teams to develop and qualify new technologies, improve yield and reliability, and ensure product readiness for ramp. The engineer applies expertise in process integration, DOE, quality systems, and failure analysis to drive innovation in RF-SiP and CPI applications while mitigating technical risks and supporting global NPI efforts.

FablessOnsiteHardware Engineering

Key Responsibilities

  • Support development of advanced technologies for Si / GaAs backend interconnect, passivation, RDL, bump and flip chip packaging (CPI)
  • Monitor and improve existing processes to improve yield, quality, and throughput, thereby increasing efficiency and product reliability
  • Support new pioneering singulation development
  • Conversant with substrate and assembly packaging processes for RF-SiP (Radio Frequency-System in Package) applications
  • Formulate industry-leading design guidelines which involves a comprehensive approach that incorporates lessons from past failures and acknowledges manufacturing constraints
  • Create, conduct, and analyze Design of Experiments (DOE) for development activities, especially those that relate to bump/die sort quality, yield and impact on CPI
  • Interface with foundries and OSATs for direct project management of critical programs
  • Understand process details, SPC, Control plans, OCAPs, FMEAs, PCN, CARs and Quality metrics. Conduct audits, benchmarking and drive best practice methodologies to proactively prevent quality excursions as the technology ramps
  • Resolve quality, yield and manufacturing problems with structed methods of problem solving

Requirements

  • Master’s Degree or equivalent in Mechanical / Materials / Chemical Engineering. PHD Preferred
  • 10+ years of experience desired in electronics packaging in related environments, especially RF module industry
  • At least 5 years direct experience in process engineering, product integration or quality management at tier 1 foundries, or assembly sub-contractors
  • Solid technical understanding of full range of Semiconductor packaging materials, material interactions, processes, dominant failure mechanisms and analytical techniques
  • Good knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI)
  • Understanding of package/product qualification and reliability methods and failure analysis is required
  • Familiarity with PCB design and layout tools preferred
  • Understanding of statistics, control methodology, FMEA, analytical trouble shooting in a factory environment is required
  • Excellent communication skills
  • Willingness to travel internationally, typically once per quarter
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related