Micron Technology

EDE-SG Equipment Development Senior Engineer/Engineer (Dry Etch)

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 2 months ago

About the role

AI summarised

Join Micron Technology to drive innovation in memory and storage solutions by developing, optimizing, and maintaining advanced dry etch equipment for next-generation 3D NAND nodes.

IDMOnsiteSTPG

Key Responsibilities

  • Set up equipment and/or CIP hardware for evaluation by the process development team to support early introduction, maturity, and adoption of 3D NAND nodes.
  • Collaborate with Fab layout and facility teams to ensure flawless installation and operation of equipment.
  • Develop and optimize existing equipment hardware to meet the efficiency requirements of advanced 3D NAND parts.
  • Translate future technology needs into clear equipment development requirements by engaging with peers on upcoming nodes.
  • Build and implement advanced equipment monitoring and control methodologies.
  • Lead teams or suppliers on complex projects to mature equipment technology for technical advantage, cost, and efficiency.
  • Serve as a technical expert within Micron, advising senior management on equipment development improvements and leading innovation projects.

Requirements

  • Bachelor’s or Master’s Degree in Mechanical, Chemical, Electrical/Electronic, or Material Science with no less than 3 years of relevant experience, OR a PhD in a related field.
  • In-depth understanding of dry etch equipment operation, working principles, troubleshooting, and tool installation procedures.
  • Proven ability to prioritize and manage multiple projects simultaneously while efficiently applying resources.
  • Remarkable oral and written communication skills for global technical expression.
  • Ability to identify and resolve safety hazards while strictly following procedures (lockout, chemical safety, lifting techniques).
  • Maintain and publish roadmaps defining work/CIPs needed to advance toolsets through EMI levels toward HVM transfer.