Jobfoundry
Jobfoundry
Micron Technology

NAND Design Rule Manager

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 4 weeks ago
Apply Now

About the role

AI summarised

Lead a talented team in the capacity of Manager for NAND Design Rule/Process Integration, supporting both development and large-scale production of advanced 3D NAND technologies. This role is critical for ensuring high quality, accurate design-rule and PDK results, and maintaining strict documentation across R&D and production efforts.

IDMOnsiteSTPG

Key Responsibilities

  • Lead the release of design rules and PDK deliverables, coordinating DRC waivers, mask definitions, and mask reviews for R&D and production.
  • Own program execution from kickoff through end-of-life for assigned projects.
  • Partner cross-functionally with Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, and Quality & Reliability to guide new 3D NAND generations.
  • Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
  • Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to address layout- or database-related process issues.
  • Build and evaluate test structures to generate data for next-generation devices and assess process margin on current technologies.
  • Synthesize complex technical problems, clearly communicating status, risks, and resolutions across functions and management levels.
  • Define and track sub-milestones within PDK/DBR/TO schedules, ensuring targets are met through cross-team coordination.

Requirements

  • PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; OR Master’s degree with 8+ years; OR Bachelor’s degree with 13+ years in the semiconductor industry.
  • Direct experience working with PDK, design rules, and layout, including small layout assignments.
  • Proficiency in CAD software such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE or their equivalents.
  • Solid understanding of semiconductor device physics and VLSI silicon processing and integration flow.
  • Understanding of 3D NAND process flow and major NAND components (e.g., bit-line sensing, word-line driver, data path, and analog circuits).
  • Demonstrated ability to resolve complex issues and communicate clearly under pressure.
  • Familiarity with CAD group interactions, data post-processing, and data transfer from built databases to reticles.