About the role

AI summarised

The Staff DFT Engineer at AMD will drive test development and quality assurance for advanced MPSoC designs at 7nm and beyond. This role involves leading DFT architecture definition, implementation, and validation for complex SoCs, collaborating across design, test, and manufacturing teams to ensure production readiness. The engineer will own test development for digital logic, debug scan and MBIST issues, and contribute to yield improvement and continuous learning within a globally distributed team.

FablessOnsiteEngineering

Key Responsibilities

Partner closely with RTL design teams to define, review and ensure correct insertion of DFT architectures across SoC and IP designs
Develop, implement and verify robust DFT schemes for hard IPs and FPGA-based designs
Own test development for digital logic using scan compression and multiple fault models, including stuck-at, transition and path-delay
Develop and validate MBIST architectures and patterns to ensure high coverage and production readiness
Lead debugging of scan, MBIST and pattern-related issues on bench and ATE, driving root-cause analysis and resolution
Collaborate with NPI, Test Engineering and Product teams to deliver high-quality, production-ready test content on schedule
Support diagnosis and yield improvement efforts throughout the product lifecycle
Design and implement firmware-driven, cost-effective test strategies with built-in diagnostic capabilities
Optimize test methodologies to improve coverage, reduce test cost and enhance overall product quality
Contribute to continuous improvement by mentoring team members and sharing best practices

Requirements

Experience designing and implementing complex, chip-level DFT architectures for advanced SoCs
Hands-on experience with DFT implementation, including Scan and Scan Compression, at IP and SoC levels
Experience using DFT and ATPG tools across stuck-at, at-speed and path-delay fault models
Proficiency in RTL logic design using Verilog, with working knowledge of synthesis and static timing analysis
Experience developing testbenches and running simulations in RTL, gate-level and SDF environments
Working knowledge of MBIST architectures and pattern development
Familiarity with FPGA design and synthesis flows
Exposure to post-silicon debug, bench setup and ATE-based validation
Comfortable working in Linux environments and using scripting languages such as Perl, Tcl or Python
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field
Formal education or training with a focus on digital design, DFT or test methodologies
Tessent Scan, ATPG or MBIST certifications are a plus