About the role
AI summarisedSenior technical lead responsible for end-to-end packaging technology integration, from wafer pre-assembly and bumping through to high-volume manufacturing and OSAT management for RF Front End Modules.
FablessOnsiteHardware Engineering
Key Responsibilities
- Drive development and integration of Si and GaAs packaging processes from wafer-level interconnect and RDL through Cu pillar bumping and flip-chip assembly
- Lead and qualify wafer singulation technologies including stealth dicing and plasma dicing with ownership of die strength and reliability tradeoffs
- Develop and maintain packaging design rules aligned with manufacturing and reliability constraints
- Own end-to-end technology integration into products including risk assessment, mitigation, and release readiness
- Drive SPC, FMEA, change control, and audits to ensure smooth ramp and HVM stability
- Plan and execute DOE to optimize bump, die sort, yield, and CPI performance
- Lead failure analysis, root cause resolution, and reliability learning during NPI and HVM
- Explore and evaluate future 2.5D packaging technologies for feasibility and manufacturing readiness
Requirements
- Master’s degree in Mechanical, Materials, Chemical, or Electrical Engineering; PhD preferred
- Minimum 6 years of relevant semiconductor packaging experience with a Bachelor's, or 10+ years preferred
- Hands-on experience in wafer pre-assembly and wafer BE including Cu pillar bumping and wafer singulation
- Demonstrated ability to resolve wafer-level yield, die integrity, and reliability issues impacting downstream assembly
- Strong understanding of packaging materials, process interactions, failure mechanisms, and reliability
- Experience interfacing with tier-1 foundries and OSATs for technology qualification
- Working knowledge of industry standards such as IPC, JEDEC, IEEE, and ISO
- Solid foundation in statistics, SPC, and FMEA methodologies
- Willingness to travel internationally approximately once per quarter