About the role
AI summarisedThe Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM). This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes.
IDMOnsiteSTPG
Key Responsibilities
- Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
- Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
- Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
- Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
- Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
- Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.
Requirements
- Proven ability to define probe coverage intent and translate design/process risks into manufacturable probe strategies.
- Experience spanning pre‑silicon staging through high‑volume manufacturing (HVM).
- Ability to collaborate closely with Design, DFT, DV, Process Integration, and Backend Test teams.
- Proficiency in silicon and device‑level characterization (parametric behavior, margins, trims).
- Experience in establishing and sustaining probe test flows.
- Strong analytical skills to correlate early silicon behavior with probe results and identify gaps.