AMD

Senior Staff Silicon Design Engineer - RTL

AMD
Fabless SemiconductorSingapore, SingaporeOnsitePosted 1 day ago

About the role

AI summarised

AMD is seeking a Senior Staff Silicon Design Engineer to join the SerDes Technology group, focusing on the architecture, RTL design, and implementation of next-generation high-speed interface technologies.

FablessOnsiteEngineering

Key Responsibilities

  • Architecture, design, and development of complex digital logic blocks in leading edge technology nodes
  • Perform test bench development and functional verification of developed digital logic blocks
  • Perform post silicon validation, testing and debug of block functionality on prototype silicon
  • Work closely with system architect, project manager, design and verification teams to develop design specifications documents
  • Develop verification plans and validation test plans

Requirements

  • Bachelor or Masters Degree in Electronic Engineering
  • Experience in ASIC/digital IC development with completion of several complex ASIC or IC production tapeouts
  • Proven experience across RTL design in Verilog/VHDL and functional verification
  • Strong understanding of the end‑to‑end digital ASIC design flow, from RTL architecture through sign‑off methodologies
  • Knowledge of UVM and SystemVerilog language
  • Experience using AI‑assisted tools to support engineering productivity and workflow efficiency
  • Excellent problem solving and debugging skills