About the role
AI summarisedThis senior staff role focuses on the design and verification of analog mixed-signal circuit blocks for AMD's SERDES IP, including PLLs, clock distribution, and transceiver components. The engineer will lead design reviews, collaborate with validation teams on silicon evaluation, and contribute to high-speed analog designs in advanced process nodes. The position requires deep expertise in analog circuit design and experience with cutting-edge semiconductor technologies.
FablessOnsiteEngineering
Key Responsibilities
- Circuit design of wireline transceiver building blocks (PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.)
- Conduct peer reviews of circuit design and verification results
- Working with validation team to evaluate silicon results
Requirements
- Extensive experience with high speed analog design with blocks like ADC, PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer
- Experience with latest process technologies like 7nm or below FinFET technology
- Bachelors/Masters/Phd Degree in Electronic Engineering
- Deep understanding of analog design
- Ability to lead, attend, and present at design review meetings with teams worldwide