About the role
AI summarisedSenior Staff Verification Engineer responsible for leading verification efforts of DDR interfaces including DDR5, LPDDR5, and DFI for server memory products. The role involves driving verification strategies, collaborating with cross-functional teams, ensuring FW/Bios/SW alignment, and supporting pre-silicon and post-silicon validation. Requires expert-level SystemVerilog, UVM, scripting, and multiple tape-out experiences in high-performance server memory environments.
FablessOnsiteEngineering
Key Responsibilities
- Lead and collaborate with team in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products
- Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
- As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
- Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Requirements
- Developed and implemented SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems
- Provided technical leadership across multiple teams, driving cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware
- Built VIPs and BFMs for memory interfaces from scratch
- GLS, NLP, XPROP simulation experience
- Strong proficiency in system verilog assertions, constraints and coverage
- Worked in formal verification methods, with proven record of tool usage beyond the standard apps
- Working knowledge of DFT flows
- Excellent communication, management, and presentation skills
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
- Bachelor’s +12 years or Master’s degree + 8 years in related discipline
- Expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl
- Proven track record of multiple tape-out experiences and successful verification sign-offs in a high-performance server memory environment