Micron Technology

Dry Etch MTS/Principal Engineer, Process Development SG, Advanced NAND

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 1 week ago

About the role

AI summarised

Join a groundbreaking Next Generation NAND research and development Dry Etch team as an MTS/Principal Engineer. This role involves leading innovation in Dry Etch technology, developing processes to meet stringent structural and electrical specifications, and collaborating cross-functionally with teams like Wet Etch, CVD, Diffusion, Lithography, and CMP to achieve program and yield targets for advanced NAND products.

IDMOnsiteSTPG

Key Responsibilities

  • Lead innovation in Dry Etch technology and drive essential module advancement for Next Generation NAND.
  • Develop and innovate dry etch processes to meet demanding structural and electrical specifications.
  • Collaborate with hardware teams to define the equipment roadmap for current and upcoming generation NAND products.
  • Lead cross-functional teams to troubleshoot and solve complex structural problems encountered during development.
  • Present detailed process and technology roadmaps for current and future technology nodes to stakeholders.
  • Proactively identify potential future process issues and develop robust mitigation plans.
  • Mentor less experienced engineers and contribute to the Technical Leadership Program.

Requirements

  • 6-10 years’ experience in dry etch process development within an R&D environment transitioning into manufacturing.
  • 4-5 years of applicable experience in NAND, DRAM, or Logic module development involving cross-functional team projects.
  • Strong knowledge of plasma physics, plasma chemistry, transport, or surface phenomena.
  • Demonstrated leadership in technical problem-solving and experience managing complex technical projects.
  • In-depth understanding of various plasma dry etch reactor types (e.g., RF sources, chemistries).
  • Expertise in statistical process control and advanced data analysis.
  • Proven experience solving scalability issues in deep high aspect ratio silicon/dielectric etches using advanced pulsing schemes.