About the role
AI summarisedThis project focuses on Cell Wafer Level Reliability (cWLR) in a semiconductor wafer fabrication environment, applying Machine Learning to predict intrinsic cell reliability metrics. The intern will contribute to developing faster, scalable methods for intrinsic issue detection and quality control in High Volume Manufacturing (HVM).
IDMOnsiteFront End
Key Responsibilities
- Learn advanced NAND cell wafer-level reliability testing flows and methodologies
- Understand semiconductor reliability failure mechanisms and device physics
- Partner with cross-site and cross-functional teams to develop and implement cWLR test programs aligned with shift-left initiatives
- Support NAND product characterization, experimentation, and data analysis to develop cWLR solutions for product issues
- Apply Machine Learning techniques to model and predict NAND cell intrinsic reliability performance
- Analyze large datasets to enable smart sampling strategies and early intrinsic risk detection
Requirements
- Bachelor's/Master's Degree in Electrical/Electronic Engineering, Microelectronic preferred
- Problem solving skills
- Data analytics skills
- Python proficiency
- Interest in semiconductor reliability testing flows
- Willingness to commit to a minimum 5-month duration (July to November 2026)