About the role
AI summarisedAMD is seeking a senior Verification Engineer to lead verification efforts for DDR5, LPDDR5, and DFI memory interfaces in server products. The role involves developing testbenches, collaborating with hardware/firmware/software teams, and ensuring alignment across silicon, firmware, BIOS, and software layers. The ideal candidate will have deep expertise in SystemVerilog, UVM, and memory protocol verification, with strong communication and mentoring abilities.
FablessOnsiteEngineering
Key Responsibilities
- Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
- Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
- Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Requirements
- Built VIPs and BFMs for memory interfaces from scratch (preferrable)
- GLS, NLP, XPROP simulation experience is preferable
- Strong proficiency in system verilog assertions, constraints and coverage.
- Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
- Excellent communication, management, and presentation skills.
- Bachelor’s or Master’s degree in related discipline