About the role

AI summarised

Senior Staff Product Development Engineer at AMD, responsible for characterizing next-generation Memory Controller IPs and Memory Subsystem for DDR/LPDDR protocols. Role involves post-silicon validation, bench testing, data analysis, and cross-functional collaboration in a semiconductor environment.

FablessFull-time{'name': 'Engineering'}

Key Responsibilities

Gain expertise into the AMD SoC architecture to characterize next generation Memory Subsystem (Controller, PHY and IO) for various supported protocols such as DDR4, LPDDR4, DDR5, LPDDR5, DDR6 and LPDDR6.
Understand Pattern development nuances and guide the team for bench data collection and debug with lab instruments when necessary.
Work closely with cross functional teams from design and firmware side to identify key new features, firmware stability and ensure proper test coverage for the same.
Drive continuous improvement initiatives on automated test scripts and test frameworks for efficient data collection, test-time optimization and data analysis.
Stay updated with the latest developments in Memory specifications and trends to inform product strategy and direction
Statistical data analysis to post process volume results for data correlation across Process corners and outlier analysis.
Responsible for isolating the issue to a specific area such as test gaps, SW bug, silicon bug, or process deviation using bench setup and instill good debug practices in the team.
Drive cross-functional discussions to address the issues uncovered from debugs and collaborate for ensuring screens are in-place for gaps identified.

Requirements

Extensive years of experience into post-silicon validation with strong background on SoC validation and system level testing.
Technical leadership experience leading a small group of senior engineers.
Strong understanding of ARM SoC architecture and Memory protocols such as DDR5 and LPDDR5.
Experienced on bench testing and debug skills with lab instruments usage.
Proficiency in using test equipment such as oscilloscopes, logic analyzers and protocol analyzers.
Experienced in Linux environment, data analysis and scripting languages (e.g. Python, Perl) for automation and data processing.
Strong communication and leadership skills, including data presentation and ability to work well in a group environment that spans across continents.
Experience with AMD/Xilinx Vivado and FPGA design flow is a plus.
BS in EE, CS, ECE or related field; MS preferred.