About the role
AI summarisedStaff Verification Engineer at AMD, responsible for verification of DDR memory interfaces (DDR5, LPDDR5/6, DFI) for server products. The role involves developing verification plans, collaborating with cross-functional teams, and supporting post-silicon debug. Requires expertise in SystemVerilog, UVM, and scripting languages.
FablessFull-time{'name': 'Engineering'}
Key Responsibilities
- Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
- Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
- Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
- Knowledge sharing and other contributions to verification methodology
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Requirements
- Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
- Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
- Built VIPs and BFMs for memory interfaces from scratch (preferrable)
- GLS, NLP, XPROP simulation experience is preferable
- Strong proficiency in system verilog assertions, constraints and coverage.
- Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
- Excellent communication, management, and presentation skills.
- Bachelor's or Master's degree in related discipline