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AMD

Senior Silicon Design Engineer – RTL

AMD
Fabless SemiconductorSingapore, SingaporeFull-time1 months ago
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About the role

AI summarised

Senior digital design engineer at AMD's SerDes Technology group, responsible for RTL design, DFT, verification, and post-silicon validation of digital logic blocks for FPGA/ASIC SerDes/transceiver solutions.

FablessFull-time{'name': 'Engineering'}

Key Responsibilities

  • Design and development with leading edge technology nodes on digital logic blocks.
  • DFT implementation and verification.
  • Perform test bench development and functional verification of developed digital logic blocks.
  • Perform post silicon validation, testing and debug of block functionality on prototype silicon.
  • Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.

Requirements

  • Experience in ASIC or digital IC design, with hands‑on involvement in RTL development (Verilog/SystemVerilog) for complex digital blocks or subsystems.
  • Exposure to the front‑end digital design flow, including RTL coding, functional verification, lint/CDC checks, logic synthesis, and timing analysis.
  • Experience contributing to one or more ASIC or FPGA tapeouts, either at block or subsystem level.
  • Familiarity with DFT concepts and flows; hands‑on experience is a plus but not mandatory.
  • Exposure to post‑silicon validation, testing, or debug, with an interest in understanding silicon behaviour and root‑cause analysis.
  • Background in high‑performance or high‑speed digital designs (e.g., SoC interconnects, memory interfaces, I/O subsystems, data‑path logic) is advantageous.
  • Knowledge of SystemVerilog and UVM is a plus.
  • Strong problem‑solving skills, willingness to learn new domains (e.g., SerDes/transceiver logic), and ability to collaborate effectively with cross‑functional teams.
  • Bachelor or Masters Degree in Electronic Engineering.