About the role

AI summarised

Senior Analog Layout Engineer at Marvell, a semiconductor company. The role involves working with global engineering teams to perform analog/mixed-signal IC layout using Cadence Virtuoso, collaborating closely with analog designers, and contributing to full project lifecycle. Requires hands-on experience in physical design flow, layout techniques, and strong teamwork skills.

FablessFull-timeGeneral

Key Responsibilities

Work closely with global engineering teams across Argentina, Singapore, the U.S., and Europe, contributing to collaborative, internationally distributed projects.
Support layout verification and simulation activities using Cadence Virtuoso, partnering closely with analog designers to iteratively refine, debug, and improve layouts until design specifications are met.
Participate in projects ranging from a few months to approximately 18 months, with flexibility to move between projects as priorities evolve and new opportunities arise.
Engage in regular one-on-one and team meetings with your paired analog designer, ensuring clear communication, effective information sharing, and smooth day-to-day collaboration in line with Marvell's teamwork-driven culture.
Contribute as an active member of the layout and project teams throughout the full project lifecycle, attending routine technical meetings to provide progress updates and discuss layout-related issues.
With guidance from senior engineers, assist in identifying, presenting, and addressing layout challenges, helping communicate solutions or learnings encountered during the development of advanced technologies.

Requirements

Hands-on experience or academic exposure to analog or mixed-signal IC layout, including familiarity with physical implementation layers (diffusion, poly, metal, vias), beyond schematic-level design.
Exposure to layout of high-speed or precision analog circuits, gained through coursework, internships, or early-career project work.
Working knowledge of the physical design flow, including floorplanning, layout implementation, and basic verification steps such as DRC and LVS.
Experience contributing to layouts at different hierarchy levels, such as individual devices, small cells, or functional blocks, with guidance from senior engineers.
Awareness of key analog layout techniques, such as matching, symmetry, guard rings, shielding, and basic parasitic considerations, with willingness to learn and apply best practices.
Good communication and teamwork skills, enabling effective collaboration with analog designers, verification engineers, and global teams in a learning-focused environment.
A solid foundation in electrical engineering concepts, typically through a degree in Electrical or Electronic Engineering, with basic understanding of analog circuits and device behavior.