About the role
AI summarisedJoin AMD to drive product quality and time-to-market as a Senior Test Engineer. This role is critical in enabling the availability of FPGAs, SoCs & ACAPs by developing robust ATE test programs and collaborating on yield/quality improvement initiatives.
FablessOnsiteEngineering
Key Responsibilities
- Develop ATE test programs for FPGA & SoCs products, including constructing/enhancing test methods and integrating timings/levels into the test flow.
- Collaborate with test pattern developers during New Product Introduction (NPI) by generating, debugging, and implementing new test patterns.
- Work with product/yield engineers to implement new test requirements for yield and quality improvements.
- Drive productivity improvement and cost reduction activities, such as test time reduction and multi-site development.
- Analyze large test datasets to drive yield improvement, failure analysis, and continuous optimization, including building automated dashboards and reports.
- Manage and execute complex test cost reduction projects and New Product bring up.
Requirements
- Bachelor’s or master’s degree in Electronics Engineering
- Proven analytical and problem-solving skills.
- Effective communication and presentation skills in oral and written English.
- Ability to work effectively in cross-functional teams.
- Strong understanding of test concepts and new product development cycle (implied by experience level).
- 5 or more years of ATE test program development experience (Preferred, but critical for seniority).