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AMD

Staff Verification Engineer - Silicon Design

AMD
Fabless SemiconductorSingapore, SingaporeOnsitePosted 5 days ago
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About the role

AI summarised

Join our team to drive verification efforts for cutting-edge server memory products, focusing on advanced DDR interfaces including DFI, DDR5, and LPDDR5/LPDDR6. This role requires deep technical expertise in memory protocols and strong cross-functional collaboration skills.

FablessOnsiteEngineering

Key Responsibilities

  • Collaborate with verification engineers on the development and execution of verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
  • Analyze the PHY's interaction within the complete system, including HW (Silicon), FW, BIOS & SW, ensuring alignment to enable all memory interface features.
  • Support Post-Si teams in debugging and resolving Product Performance, Power, and functional issues.

Requirements

  • Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.
  • Bachelor’s or Master’s degree in a related discipline.
  • Excellent communication and presentation skills, demonstrated through technical publications or briefings.
  • Aptitude for collaboration among top-tier engineers and willingness to mentor the team.
  • Ability to understand and debug complex memory protocols (DFI, DDR5, LPDDR5/LPDDR6).