About the role
AI summarisedSenior/Lead Research Engineer role at IME focused on developing advanced packaging platforms including fan-out wafer-level packaging (FOWLP), 2.5D interposer, and 3D chip stacking for heterogeneous integration. The position involves hands-on cleanroom work, leading capability development projects, mentoring junior engineers, and collaborating with cross-functional teams and external stakeholders.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- Develop advanced packaging technology platforms (fan-out packaging, 2.5D interposer and 3D stacking) capabilities and novel process integration approaches for heterogeneous chiplets integration
- Work with design and process module teams to establish design rules and PDK for advanced packaging technologies
- Engage and manage internal and external stakeholders for project activities execution and provide timely updates on schedule and deliverables
- Collaborate with cross-functional teams such as design, Unit process team, yield improvement, and external partners, including materials, equipment, customers and universities, to identify technology gaps, define technology roadmap and drive the development
- Inspire and mentor students in semiconductor technology, contributing to workforce development in advanced packaging
- Mentoring junior engineers, influencing without authority, and ownership of module roadmaps
Requirements
- Bachelor's or Master's in Materials Science & Engineering, Mechanical, Chemical, Electronics/ Electrical & Computer Engineering, Physics, Chemistry or a closely related field
- 5-10 years of experience in semiconductor experience with expertise in Cu backend integration and exposure to advanced packaging technologies (flip-chip, FOWLP, 2.5D/3D, TSV, hybrid/fusion bonding)
- Broad hands-on knowledge of one or more unit processes—such as lithography, etch (damascene, TSV via-last/middle); deposition (ALD/CVD/PVD, including high-AR barrier and seed layers); electroplating and alternative via-fill materials, CMP for hybrid bonding; fusion/hybrid bonding; wafer thinning; and dicing—is preferred
- Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments
- Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab)
- NPI to HVM ramp experience: process window definition, control plans, and yield/cost improvement through pilot to high-volume manufacturing (foundry/OSAT)
- Reliability & standards: working knowledge of JEDEC/IPC/JESD (e.g., HTS, TC, HAST, BLR, EM), and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX)
- Excellent written and verbal communication abilities
- Demonstrated ability to manage multiple projects and priorities in a research and translational environment
- Able to work effectively with multi-ethnic, multicultural teams and to build inclusive, high-performing teams