About the role
AI summarisedSenior Physical Design Engineer at Marvell, a semiconductor company, responsible for block-level physical design of complex chips using EDA tools like Cadence and Synopsys, including synthesis, place and route, timing analysis, and power grid verification. The role involves working with a global team to triage workflows and ensure design readiness for next stages.
FablessFull-timeGeneral
Key Responsibilities
- Work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
- Work hands-on to triage workflows, whether running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip.
- Analyze performance by running timing analysis.
- Verify a robust power grid by performing EMIR analysis.
- Review completed runs for errors or create optimizations from successful runs.
Requirements
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below).
- Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compiler, IC Compiler and Fusion Compiler.
- Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous.
- Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous.
- Enjoy learning by doing the work and having access to guides and a mentor.
- Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.