About the role
AI summarisedJoin a high-end test engineering team delivering test solutions for Data Center New Product Introduction (NPI) within the Product Engineering Organization. This role involves providing technical leadership for System Level Test (SLT) of Integrated Voltage Regulator (IVR) to meet NPI milestones and KPIs, bringing new products from first silicon to High Volume Manufacturing (HVM).
FablessOnsiteEngineering
Key Responsibilities
- Provide leadership to meet business milestones, cost, and quality targets in the GPU system level test area.
- Drive the IVR SLT swim lane from pre-silicon, ASIC initial bring up through to HVM.
- Solve complex, novel, and non-recurring engineering problems; initiate significant changes to existing processes/methods.
- Conduct engineering evaluations and analysis to qualify cutting-edge IVR for HVM and drive closure of GPU production issues.
- Profile or characterize Power Integrity (PI), voltage droop, or power delivery issues observed on SLT platforms in collaboration with board/silicon designers.
- Provide technical supervision or mentoring to junior engineers.
- Upscale overall team capabilities on low-level system debug for AMD data center product families.
Requirements
- Proficient understanding of High Power Delivery (above 1kW) design.
- Knowledge of power capacitors and inductors, buck/boost converters, and IVR (Integrated Voltage Regulator).
- Broad understanding of silicon VFT (Voltage/Frequency/Temperature) behavior, on-die silicon power integrity, and system level power management.
- Strong technical, analytical, leadership, and problem-solving skills.
- Ability to work cross-functionally with Silicon/Board/Power design, Product & Test Engineering, and Customer Quality teams.
- BS/MS in Electrical Engineering, Computer Engineering, or comparable disciplines.