About the role
AI summarisedJoin the AMD SerDes Technology Group to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. This role involves hands-on analog/mixed-signal layout design to support the future connectivity of AMD CPU and GPU products.
FablessOnsiteEngineering
Key Responsibilities
- Layout design of high speed and high performance SerDes analog mixed signal circuits according to project requirements.
- Perform block-level physical implementation including floor-planning, power distribution network design, and clock/signal routing.
- Execute analog and mixed signal transistor-level layout.
- Participate in post-layout circuit performance analysis.
- Contribute to block/IP/chip level integration activities.
- Estimate realistic schedules, track progress, and report status clearly.
- Define and contribute to layout methodology and flow.
- Drive layout productivity improvement initiatives, such as pcell development and automation.
Requirements
- Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.
- Passion for high-speed layout design with innovative problem-solving approaches.
- Strong analytical and problem-solving skills.
- Experience collaborating with engineers across different sites/time zones.
- Proficiency in analog and mixed-signal layout fundamentals.
- Familiarity with physical design verifications (LVS/DRC/ERC/ANT/ESD, etc.).