About the role

AI summarised

The Senior Engineer, Physical Design role at Marvell involves hands-on work in the physical design of complex chips, including running RTL through synthesis and place-and-route tools, performing timing and power integrity analysis, and verifying design readiness for sign-off. The role requires collaboration with a global team to improve design methodology and troubleshoot workflows. Candidates must have a strong foundation in EDA tools and physical design principles for advanced process nodes.

FablessOnsite

Key Responsibilities

Work with a global team on the physical design of complex chips
Develop and improve methodology for an efficient and robust design process
Triage workflows by running RTL code through synthesis and place and route (PnR) tools
Analyze performance by running timing analysis
Verify a robust power grid by performing EMIR analysis
Create optimizations from successful runs
Ensure database readiness for sign-off checks
Volunteer for learning opportunities and raise hand for new experiences

Requirements

Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field
3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)
Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compiler, IC Compiler and Fusion Compiler
Working knowledge of static timing analysis tools such as Tempus or PrimeTime
Working knowledge of EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Enjoy learning by doing the work and having access to guides and a mentor
Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before