A*STAR

Lead Research Engineer, Smart Operation and Planning (FAB), IME

A*STAR
ResearchSingaporeOnsitePosted 6 days ago

About the role

AI summarised

Lead research engineer responsible for end-to-end fab planning and smart factory initiatives at IME. Owns KPI frameworks, capacity models, layout optimization, and digital twin deployment to drive cycle time, throughput, and equipment utilization improvements across semiconductor R&D operations.

ResearchOnsiteInstitute of Microelectronics

Key Responsibilities

  • Define, establish, implement, and own a Fab KPI framework: OTD, cycle time (CT), WIP, inline pace / throughput, move rate, schedule adherence, equipment utilization, DPML, hold lot aging, rework/scrap, WIP turns, and forecast accuracy
  • Design and own live dashboards with tiered visual management (daily/weekly/etc) in order to set targets, guardrails, and escalation paths (e.g., CT breach, bottleneck loading, WIP caps)
  • Establish KPI definitions, data lineage, and governance to ensure single source of truth; run regular ops reviews with variance/root-cause analytics and action closure tracking
  • Build capacity models by workcenter/tool family (bottleneck and non‑bottleneck) with tool states, product mix, and modelled downtime
  • Lead medium- and long-range capacity planning, including what‑if scenarios (new products / developments, recipe changes, capex adds, PM extensions)
  • Optimize dispatching policies for WIP flows (e.g., FIFO, drum‑buffer‑rope) to stabilize bottlenecks and reduce CT variability
  • Partner with Equipment team for capability roadmaps (de-bottlenecking, redundancy, chamber matching, clone strategy)
  • Lead fab/layout planning - bay/aisle constraints, tool placement, line balancing, utilities and material flow to minimize travel, WIP touches, and cross‑traffic
  • Maintain up‑to‑date floor maps and capacity heatmaps and define staging strategies (kitting, Kanban, supermarkets) to de‑risk starvation/overfeeding at bottlenecks
  • Implement MES integration for lot movement policies, WIP caps (Littles' Law), dispatch lists, and shop‑floor visibility
  • Implement and drive digital twin / simulation for scenario planning: mix shifts, tool downs, and new line introductions
  • Lead and develop the team by setting clear goals and encouraging upskills in analytics, simulation, and scheduling

Requirements

  • Degree in Industrial/Manufacturing/Systems/Mechanical/Electrical Engineering or related field
  • 5–10+ years in semiconductor fab planning/Ops/scheduling
  • Strong command of operations analytics and queueing theory
  • Hands‑on experience with MES/APS and simulation tools
  • Data fluency: SQL, Excel/Power Query, Power BI/Tableau preferred for modeling
  • Excellent written and verbal communication; proven cross‑functional leadership in fast‑paced environments