About the role
AI summarisedThe focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s SerDes IP, ensuring no bugs in the final design. This role requires a passion for modern, complex SerDes architecture, digital design, and verification.
FablessOnsiteEngineering
Key Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand new features requiring verification.
- Build comprehensive test plan documentation covering interactions with hardware, firmware, and software driver use cases.
- Estimate the time needed to write new feature tests and any required changes to the test environment.
- Build directed and random verification tests for SerDes IP features.
- Debug test failures to determine root cause, collaborating with RTL and firmware engineers to resolve design defects.
- Review functional and code coverage metrics, modifying or adding tests to meet coverage requirements.
Requirements
- Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.
- Strong analytical and problem-solving skills.
- Passion for modern, complex SerDes architecture, digital design, and verification.
- Excellent communication skills and experience collaborating across different sites/timezones.
- Willingness to learn and readiness to take on complex technical problems.