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Qualcomm

Packaging Technology Integration, Staff Engineer

Qualcomm
Fabless SemiconductorSingapore, Central Singapore, SingaporeOnsitePosted 1 week ago
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About the role

AI summarised

Join the team focused on RF Front End Modules for Cellular and Wireless Data markets. This senior technical role owns end-to-end packaging technology and product integration, spanning technology development, chip-to-package co-design, NPI, High Volume Manufacturing (HVM) interaction, and customer lifecycle support to deliver robust and scalable solutions.

FablessOnsiteHardware Engineering

Key Responsibilities

  • Serve as a senior technical lead in a global, cross-functional matrix, driving technology readiness and product timelines.
  • Drive development and integration of Si and GaAs packaging processes from wafer-level interconnect through flip-chip assembly.
  • Lead and qualify wafer singulation technologies, including stealth dicing and plasma dicing, managing die strength and yield tradeoffs.
  • Own end-to-end technology integration into products, including wafer-level and package-level risk assessment and mitigation.
  • Serve as the technical interface to OSATs, leading technology transfer and new OSAT bring-up from development through production.
  • Drive SPC, FMEA, PCN, change control, and audits to ensure smooth ramp and HVM stability.
  • Own yield, quality, throughput, and reliability improvements to ensure successful ramp and sustained HVM product integrity.
  • Lead failure analysis, root cause resolution, and reliability learning during NPI and HVM.
  • Support customer NPQ, RMA analysis, and direct technical communication.

Requirements

  • Master’s degree in Mechanical, Materials, Chemical, or Electrical Engineering (PhD preferred).
  • 10+ years’ experience in semiconductor packaging, preferably RF modules / SiP.
  • Demonstrated ownership across technology development, NPI, HVM, and customer support.
  • Hands-on experience in wafer pre-assembly / wafer BE, including Cu pillar or micro-bump bumping, wafer singulation, and die sort.
  • Proven ability to debug and resolve wafer-level yield, die integrity, and reliability issues impacting downstream assembly.
  • Strong understanding of packaging materials, process interactions, failure mechanisms, and reliability.
  • Hands-on experience with tier-1 foundries and OSATs.
  • Solid foundation in statistics, SPC, and FMEA.