About the role
AI summarisedAMD is seeking a talented SerDes Verification Engineer to work on verifying and validating high-speed interfaces used in advanced SoCs and chiplet designs. This role involves building UVM/SystemVerilog testbenches, running simulations, and debugging complex timing and protocol issues.
FablessOnsiteEngineering
Key Responsibilities
- Verifying and validating high-speed interfaces in advanced SoCs and chiplet designs
- Building UVM/SystemVerilog testbenches for SerDes verification
- Running simulations to evaluate signal integrity, jitter, BER, and eye diagrams
- Debugging timing and protocol issues within high-speed interfaces
- Ensuring compliance with protocols such as UCIe, PCIe, and DDR in collaboration with design and hardware teams
Requirements
- Proficiency in SerDes verification concepts
- Experience with UVM/SystemVerilog testbench development
- Strong understanding of high-speed interface protocols (UCIe, PCIe, DDR)
- Ability to analyze signal integrity and eye diagrams
- Experience debugging timing and protocol compliance issues