Jobfoundry
Jobfoundry
AMD

Staff DFT Engineer

AMD
Fabless SemiconductorSingapore, SingaporeOnsitePosted 1 month ago
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About the role

AI summarised

Join the Test Development team at AMD, playing a pivotal role in shaping how complex, high-performance MPSoC designs (at 7nm and beyond) are tested, validated, and delivered across automotive, data center, machine learning, and high-speed connectivity markets. This role offers deep, hands-on exposure to Scan, MBIST, and iJTAG test development at the intersection of design, test, and manufacturing.

FablessOnsiteEngineering

Key Responsibilities

  • Partner closely with RTL design teams to define, review, and ensure correct insertion of DFT architectures across SoC and IP designs.
  • Develop, implement, and verify robust DFT schemes for hard IPs and FPGA-based designs.
  • Own test development for digital logic using scan compression and multiple fault models, including stuck-at, transition, and path-delay.
  • Develop and validate MBIST architectures and patterns to ensure high coverage and production readiness.
  • Lead debugging of scan, MBIST, and pattern-related issues on bench and ATE, driving root-cause analysis and resolution.
  • Collaborate with NPI, Test Engineering, and Product teams to deliver high-quality, production-ready test content on schedule.
  • Support diagnosis and yield improvement efforts throughout the product lifecycle.
  • Design and implement firmware-driven, cost-effective test strategies with built-in diagnostic capabilities.
  • Optimize test methodologies to improve coverage, reduce test cost, and enhance overall product quality.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
  • Proven ability to work in a globally distributed and highly collaborative environment.
  • Strong technical ownership and proactive problem-solving mindset.
  • Experience designing and implementing complex, chip-level DFT architectures for advanced SoCs (preferred experience).
  • Hands-on experience with DFT implementation, including Scan and Scan Compression, at IP and SoC levels (preferred experience).
  • Proficiency in RTL logic design using Verilog, with knowledge of synthesis and static timing analysis.