About the role

AI summarised

The Standard Cell Library Design Engineer will design, develop, and deliver standard cell foundation IP at the transistor level for Broadcom's silicon products. Responsibilities include circuit simulation, EDA model generation and verification, regression testing, and collaboration with design teams. The role requires strong digital/mixed-signal design knowledge, familiarity with advanced process nodes, and proficiency in EDA tools and scripting languages.

FablessOnsite

Key Responsibilities

Design standard cells at transistor level
Run regression and quality checks on library deliverables
Interface with design teams to support their requirements

Requirements

Digital or mixed-signal circuit design knowledge
Understanding of cell layout or physical design
Understanding of FinFet, RibbonFet/GAA process nodes
Understanding of verilog, lef, liberty and other industry standard EDA models
Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R)
Experience with .lib syntax including NLDM/CCS/LVF is a plus
Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python is strongly desired
Bachelor's in Electrical/Electronic or Computer Engineering and 5+ years of related experience / Candidates with Masters and 3+ years of related experience / PhD in related field of studies with no experience
Singapore Citizen/PR only
Excellent written and verbal communication skills
Collaborate and work within and across teams