About the role
AI summarisedJoin the SerDes Technology group at AMD to contribute to the architecture and implementation of next-generation high-speed interface technologies. This role involves hands-on work across the entire FPGA/ASIC digital design flow, from architectural specification through post-silicon validation.
FablessOnsiteEngineering
Key Responsibilities
- Architecture, design, and development of complex digital logic blocks in leading-edge technology nodes.
- Performing DFT implementation and verification for designed blocks.
- Developing test benches and functionally verifying developed digital logic blocks.
- Conducting post-silicon validation, testing, and debugging of block functionality on prototype silicon.
- Collaborating with system architects, project managers, and design/verification teams to create design specifications, verification plans, and validation test plans.
Requirements
- Proven experience across RTL design in Verilog/VHDL, functional verification, synthesis, and DFT applied to complex high-performance designs.
- Strong understanding of the end-to-end digital ASIC design flow, from RTL architecture through sign-off methodologies.
- Ability to execute design work and contribute technically with a high general impact on the overall design.
- Innovative, highly accurate, and detail-oriented approach to engineering challenges.
- Good problem-solving and debugging skills.
- Excellent verbal and written communication skills.