AMD

Senior Staff Silicon Design Engineer - RTL

AMD
Fabless SemiconductorSingapore, SingaporeFull-time1 weeks ago

About the role

AI summarised

Senior Staff Silicon Design Engineer (RTL) at AMD, contributing to the architecture and implementation of next-generation high-speed SerDes technologies. The role involves all aspects of digital design flow from RTL to post-silicon validation in a collaborative, innovative environment.

FablessFull-time{'name': 'Engineering'}

Key Responsibilities

  • Architecture, design, and development of complex digital logic blocks in leading edge technology nodes.
  • DFT implementation and verification.
  • Perform test bench development and functional verification of developed digital logic blocks.
  • Perform post silicon validation, testing and debug of block functionality on prototype silicon.
  • Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.

Requirements

  • Experience in ASIC/digital IC development with completion of several complex ASIC or IC production tapeouts.
  • Proven experience across RTL design in Verilog/VHDL, functional verification, synthesis and DFT, applied to complex high performance design.
  • Strong understanding of the end‑to‑end digital ASIC design flow, from RTL architecture through sign‑off methodologies.
  • Excellent verbal and written communication skills. Strong interpersonal skills.
  • Problem solving and debugging skills.
  • Knowledge of UVM and SystemVerilog language.
  • Experience using AI‑assisted tools to support engineering productivity and workflow efficiency.
  • Bachelor or Masters Degree in Electronic Engineering, with years of relevant work experience.