Qualcomm

Engineer, Senior (Technology Integration - Wafer-level Packaging)

Qualcomm
Fabless SemiconductorSingapore, Central Singapore, SingaporeFull-time1 months ago

About the role

AI summarised

Senior Engineer responsible for end-to-end development, qualification, and mass-production transfer of wafer-level packaging processes at a semiconductor company. Leads technology integration projects, drives root-cause analysis, and coordinates ramp performance tracking to ensure robust manufacturability.

FablessFull-timeHardware Engineering

Key Responsibilities

  • Responsible for end‑to‑end development, qualification, and mass‑production transfer of new processes, materials, and manufacturing technologies.
  • Ensure process readiness, robust manufacturability, and smooth ramp‑up through strong cross‑functional coordination, data‑driven decision‑making, and technology leadership.
  • Initiate and participate actively in discussions on formulation of process technology innovation and release process improvement.
  • Collaborate and develop effective working relationships with technology partners to accomplish project/ task goals within committed schedule.
  • Develop new and impactful ideas, materials, solutions, and/ or procedures for product fabrication process and technology meeting the business goals and launch schedule with competitive manufacturing costs.
  • Serve as technology subject matter expert applying technical knowledge and skills in own area of expertise to address moderately complex issues in manufacturing environment.
  • Lead development of new processes, modules, or integration flows from concept to qualification and manufacturing release.
  • Define process requirements, success criteria, design‑of‑experiments (DOE), and characterization plans.
  • Drive root‑cause analyses, failure mechanism studies, and improvement loops to achieve performance, yield, and reliability targets.
  • Translate product requirements into process specifications and control strategies.
  • Co-own the technology transfer roadmap with project leader - from pilot line to high‑volume manufacturing. Adapts to shifting priorities and resources while ensuring deadlines are met.
  • Supervise and provide technical guidance to onsite process transfer activities, including documentation (PFMEA, etc), training, process replication, and equipment matching.

Requirements

  • Bachelor's or Master's degree in Engineering (Materials, Chemical, Semiconductor, etc.).
  • 3+ years of experience in process integration engineering, technology development, or a high volume manufacturing fab.
  • Broad exposure to wafer-level packaging technology and processes.
  • Demonstrated success leading cross disciplinary technology integration projects.
  • Strong skills in DOE, SPC, data analytics, FMEA, and troubleshooting.
  • Excellent communication, technical documentation, and stakeholder management skills.
  • Resourceful with critical thinking in problem solving.
  • Project and priority management skills.
  • Experience in semiconductor, MEMS, packaging, or high‑volume manufacturing.
  • Familiarity with yield engineering, reliability mechanisms, and failure analysis as well as use of statistical tools, DOE, PFCP/ PFMEA, etc.
  • Experience with scale-up from R&D → Pilot → HVM.
  • Knowledge of Lean, Six Sigma, or structured problem-solving (8D, DMAIC).
  • Able to multi-task, set priorities and meet critical deadlines. Maintain open communication.
  • Able attend training program overseas at sister's fab for up to 1 year.