About the role

AI summarised

This IC Design Engineer role focuses on the physical design and implementation of high-performance System-on-Chip ASICs at advanced process nodes (5nm/3nm/2nm). The position involves leading physical design efforts for large-scale ASICs (500-800 million gates), collaborating with RTL and physical design teams to resolve timing issues, and contributing to design flow and methodology innovation. The role requires strong technical expertise in EDA tools, scripting, and customer-facing technical support.

FablessOnsite

Key Responsibilities

Lead team in physical design implementation of large ASICs (500 to 800 million gates complexity)
Provide technical support to customers and manage customer working relationships
Utilize leading edge physical design EDA tools in projects
Collaborate with RTL and Physical Design teams to resolve timing violations through design or constraint optimization
Utilize commercial and in-house EDA tools for design and implementation of 500 ~ 800 million gate integrated circuits in 5nm/3nm/2nm process technologies
Participate in innovation, design flow and methodology development to address challenges of deep submicron processes and state-of-the-art ASIC design for computing and networking products

Requirements

Degree, Masters or PhD in Electrical/Electronics/Computer engineering
7 years or more experience in a relevant field
Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
Strong analytical problem-solving skills
Ability to collaborate in cross-functional team environments
Experience in Perl, Tcl & Python Scripting languages